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98 lines
2.4 KiB
98 lines
2.4 KiB
0 400 400 // Examples drawn from https://verilogams.com/refman/basics/index.html
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0 400 400
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0 400 400 // SCE_V_DEFAULT {0}
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0 400 400
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2 400 401 + /*
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0 401 401 | * SCE_V_COMMENT {1}
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0 401 400 | */
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0 400 400
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2 400 401 + // SCE_V_COMMENTLINE {2}
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0 401 401 | // multiple
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0 401 401 | // comment lines
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0 401 400 | // are folded
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0 400 400
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2 400 402 + //{ explicit folds
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0 402 402 | // are folded,
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0 402 400 | //} too
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0 400 400
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2 400 401 + //! SCE_V_COMMENTLINEBANG {3}
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0 401 401 | //! multiple
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0 401 401 | //! bang comments
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0 401 400 | //! are folded
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0 400 400
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0 400 400 // SCE_V_NUMBER {4}
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0 400 400 1'b0
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0 400 400 8'hx
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0 400 400 8'hfffx
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0 400 400 12'hfx
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0 400 400 64'o0
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0 400 400 0x7f
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0 400 400 0o23
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0 400 400 0b1011
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0 400 400 42_839
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0 400 400 0.1
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0 400 400 1.3u
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0 400 400 5.46K
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0 400 400 1.2E12
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0 400 400 1.30e-2
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0 400 400 236.123_763e-12
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0 400 400
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0 400 400 // SCE_V_WORD {5}
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0 400 400 always
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0 400 400
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0 400 400 // SCE_V_STRING {6}
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0 400 400 "\tsome\ttext\r\n"
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0 400 400
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0 400 400 // SCE_V_WORD2 {7}
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0 400 400 special
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0 400 400
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0 400 400 // SCE_V_WORD3 {8}
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0 400 400 $async$and$array
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0 400 400
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0 400 400 // SCE_V_PREPROCESSOR {9}
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0 400 400 `define __VAMS_ENABLE__
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2 400 401 + `ifdef __VAMS_ENABLE__
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0 401 401 | parameter integer del = 1 from [1:100];
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2 400 401 + `else
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0 401 401 | parameter del = 1;
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0 401 400 | `endif
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0 400 400
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0 400 400 // SCE_V_OPERATOR {10}
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0 400 400 +-/=!@#%^&*()[]{}<|>~
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0 400 400
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0 400 400 // SCE_V_IDENTIFIER {11}
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0 400 400 q
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0 400 400 x$z
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0 400 400 \my_var
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0 400 400 \/x1/n1
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0 400 400 \\x1\n1
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0 400 400 \{a,b}
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0 400 400 \V(p,n)
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0 400 400
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0 400 400 // SCE_V_STRINGEOL {12}
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0 400 400 "\n
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0 400 400
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0 400 400 // SCE_V_USER {19}
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0 400 400 my_var
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0 400 400
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2 400 401 + // SCE_V_COMMENT_WORD {20}
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0 401 400 | // TODO write a comment
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0 400 400
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2 400 401 + module mod(clk, q, reset) // folded when fold.verilog.flags=1
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0 401 401 | // SCE_V_INPUT {21}
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0 401 401 | input clk;
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0 401 401 |
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0 401 401 | // SCE_V_OUTPUT {22}
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0 401 401 | output q;
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0 401 401 |
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0 401 401 | // SCE_V_INOUT {23}
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0 401 401 | inout reset;
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0 401 400 | endmodule
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0 400 400
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0 400 400 // SCE_V_PORT_CONNECT {24}
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2 400 401 + mod m1(
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0 401 401 | .clk(clk),
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0 401 401 | .q(q),
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0 401 401 | .reset(reset)
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0 401 400 | );
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0 400 0 |