98 lines
1.2 KiB
Systemverilog
98 lines
1.2 KiB
Systemverilog
// Examples drawn from https://verilogams.com/refman/basics/index.html
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// SCE_V_DEFAULT {0}
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/*
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* SCE_V_COMMENT {1}
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*/
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// SCE_V_COMMENTLINE {2}
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// multiple
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// comment lines
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// are folded
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//{ explicit folds
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// are folded,
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//} too
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//! SCE_V_COMMENTLINEBANG {3}
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//! multiple
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//! bang comments
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//! are folded
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// SCE_V_NUMBER {4}
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1'b0
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8'hx
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8'hfffx
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12'hfx
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64'o0
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0x7f
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0o23
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0b1011
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42_839
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0.1
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1.3u
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5.46K
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1.2E12
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1.30e-2
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236.123_763e-12
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// SCE_V_WORD {5}
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always
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// SCE_V_STRING {6}
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"\tsome\ttext\r\n"
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// SCE_V_WORD2 {7}
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special
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// SCE_V_WORD3 {8}
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$async$and$array
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// SCE_V_PREPROCESSOR {9}
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`define __VAMS_ENABLE__
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`ifdef __VAMS_ENABLE__
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parameter integer del = 1 from [1:100];
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`else
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parameter del = 1;
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`endif
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// SCE_V_OPERATOR {10}
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+-/=!@#%^&*()[]{}<|>~
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// SCE_V_IDENTIFIER {11}
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q
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x$z
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\my_var
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\/x1/n1
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\\x1\n1
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\{a,b}
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\V(p,n)
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// SCE_V_STRINGEOL {12}
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"\n
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// SCE_V_USER {19}
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my_var
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// SCE_V_COMMENT_WORD {20}
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// TODO write a comment
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module mod(clk, q, reset) // folded when fold.verilog.flags=1
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// SCE_V_INPUT {21}
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input clk;
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// SCE_V_OUTPUT {22}
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output q;
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// SCE_V_INOUT {23}
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inout reset;
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endmodule
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// SCE_V_PORT_CONNECT {24}
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mod m1(
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.clk(clk),
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.q(q),
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.reset(reset)
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);
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