58 lines
1.4 KiB
VHDL
58 lines
1.4 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity x is
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port(
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rst : in std_logic;
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clk : in std_logic;
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d : in std_logic;
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q : out std_logic_vector;
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a, b : in std_logic;
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v : out std_logic
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);
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end x;
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architecture behavioral of x is
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signal q_i : std_logic_vector(q'range);
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begin
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v <= a when b = '1' else '0';
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gen: for j in q'low to q'high generate
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gen_first: if j = q'low generate
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variable foo : boolean := false;
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begin
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stage1: process (rst, clk) begin
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if rst = '1' then
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q_i(j) <= '0';
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elsif rising_edge(clk) then
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q_i(j) <= d;
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case a is
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when 1 =>
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when 2 =>
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when others =>
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end case;
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end if;
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end process;
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else generate
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stages: process (rst, clk)
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begin
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if rst = '1' then
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q_i(j) <= '0';
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elsif rising_edge(clk) then
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for u in 0 to 7 loop
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q_i(j) <= q_i(j - 1);
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end loop;
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end if;
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end process;
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end generate;
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end generate;
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L: case expression generate
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when choice1 =>
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when choice2 =>
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end generate L;
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end behavioral;
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