58 lines
2.2 KiB
Plaintext
58 lines
2.2 KiB
Plaintext
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0 400 400 library ieee;
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0 400 400 use ieee.std_logic_1164.all;
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0 400 400 use ieee.std_logic_arith.all;
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1 400 400
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2 400 401 + entity x is
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2 401 402 + port(
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0 402 402 | rst : in std_logic;
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0 402 402 | clk : in std_logic;
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0 402 402 | d : in std_logic;
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0 402 402 | q : out std_logic_vector;
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0 402 402 | a, b : in std_logic;
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0 402 402 | v : out std_logic
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0 402 401 | );
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0 401 400 | end x;
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1 400 400
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2 400 401 + architecture behavioral of x is
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0 401 401 | signal q_i : std_logic_vector(q'range);
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2 400 401 + begin
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1 401 401 |
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0 401 401 | v <= a when b = '1' else '0';
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1 401 401 |
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2 401 402 + gen: for j in q'low to q'high generate
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2 402 403 + gen_first: if j = q'low generate
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0 403 403 | variable foo : boolean := false;
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2 402 403 + begin
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2 403 404 + stage1: process (rst, clk) begin
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2 404 405 + if rst = '1' then
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0 405 405 | q_i(j) <= '0';
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2 404 405 + elsif rising_edge(clk) then
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0 405 405 | q_i(j) <= d;
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2 405 406 + case a is
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0 406 406 | when 1 =>
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0 406 406 | when 2 =>
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0 406 406 | when others =>
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0 406 405 | end case;
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0 405 404 | end if;
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0 404 403 | end process;
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2 402 403 + else generate
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2 403 404 + stages: process (rst, clk)
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0 404 404 | begin
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2 404 405 + if rst = '1' then
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0 405 405 | q_i(j) <= '0';
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2 404 405 + elsif rising_edge(clk) then
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2 405 406 + for u in 0 to 7 loop
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0 406 406 | q_i(j) <= q_i(j - 1);
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0 406 405 | end loop;
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0 405 404 | end if;
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0 404 403 | end process;
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0 403 402 | end generate;
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0 402 401 | end generate;
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1 401 401 |
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2 401 402 + L: case expression generate
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0 402 402 | when choice1 =>
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0 402 402 | when choice2 =>
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0 402 401 | end generate L;
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1 401 401 |
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0 401 400 | end behavioral;
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0 400 0
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