mirror of https://github.com/k3s-io/k3s
179 lines
4.2 KiB
Go
179 lines
4.2 KiB
Go
/*
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Copyright 2015 The Kubernetes Authors.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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package userspace
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import (
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"reflect"
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"testing"
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"k8s.io/apimachinery/pkg/util/net"
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)
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func TestRangeAllocatorEmpty(t *testing.T) {
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r := &net.PortRange{}
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r.Set("0-0")
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defer func() {
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if rv := recover(); rv == nil {
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t.Fatalf("expected panic because of empty port range: %#v", r)
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}
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}()
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_ = newPortRangeAllocator(*r, true)
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}
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func TestRangeAllocatorFullyAllocated(t *testing.T) {
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r := &net.PortRange{}
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r.Set("1-1")
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// Don't auto-fill ports, we'll manually turn the crank
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pra := newPortRangeAllocator(*r, false)
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a := pra.(*rangeAllocator)
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// Fill in the one available port
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if !a.fillPortsOnce() {
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t.Fatalf("Expected to be able to fill ports")
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}
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// There should be no ports available
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if a.fillPortsOnce() {
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t.Fatalf("Expected to be unable to fill ports")
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}
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p, err := a.AllocateNext()
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if err != nil {
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t.Fatalf("unexpected error: %v", err)
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}
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if p != 1 {
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t.Fatalf("unexpected allocated port: %d", p)
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}
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a.lock.Lock()
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if bit := a.used.Bit(p - a.Base); bit != 1 {
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a.lock.Unlock()
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t.Fatalf("unexpected used bit for allocated port: %d", p)
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}
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a.lock.Unlock()
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_, err = a.AllocateNext()
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if err == nil {
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t.Fatalf("expected error because of fully-allocated range")
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}
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a.Release(p)
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a.lock.Lock()
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if bit := a.used.Bit(p - a.Base); bit != 0 {
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a.lock.Unlock()
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t.Fatalf("unexpected used bit for allocated port: %d", p)
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}
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a.lock.Unlock()
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// Fill in the one available port
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if !a.fillPortsOnce() {
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t.Fatalf("Expected to be able to fill ports")
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}
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p, err = a.AllocateNext()
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if err != nil {
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t.Fatalf("unexpected error: %v", err)
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}
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if p != 1 {
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t.Fatalf("unexpected allocated port: %d", p)
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}
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a.lock.Lock()
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if bit := a.used.Bit(p - a.Base); bit != 1 {
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a.lock.Unlock()
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t.Fatalf("unexpected used bit for allocated port: %d", p)
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}
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a.lock.Unlock()
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_, err = a.AllocateNext()
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if err == nil {
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t.Fatalf("expected error because of fully-allocated range")
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}
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}
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func TestRangeAllocator_RandomishAllocation(t *testing.T) {
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r := &net.PortRange{}
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r.Set("1-100")
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pra := newPortRangeAllocator(*r, false)
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a := pra.(*rangeAllocator)
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// allocate all the ports
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var err error
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ports := make([]int, 100, 100)
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for i := 0; i < 100; i++ {
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if !a.fillPortsOnce() {
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t.Fatalf("Expected to be able to fill ports")
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}
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ports[i], err = a.AllocateNext()
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if err != nil {
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t.Fatalf("unexpected error: %v", err)
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}
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if ports[i] < 1 || ports[i] > 100 {
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t.Fatalf("unexpected allocated port: %d", ports[i])
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}
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a.lock.Lock()
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if bit := a.used.Bit(ports[i] - a.Base); bit != 1 {
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a.lock.Unlock()
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t.Fatalf("unexpected used bit for allocated port: %d", ports[i])
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}
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a.lock.Unlock()
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}
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if a.fillPortsOnce() {
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t.Fatalf("Expected to be unable to fill ports")
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}
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// release them all
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for i := 0; i < 100; i++ {
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a.Release(ports[i])
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a.lock.Lock()
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if bit := a.used.Bit(ports[i] - a.Base); bit != 0 {
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a.lock.Unlock()
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t.Fatalf("unexpected used bit for allocated port: %d", ports[i])
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}
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a.lock.Unlock()
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}
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// allocate the ports again
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rports := make([]int, 100, 100)
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for i := 0; i < 100; i++ {
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if !a.fillPortsOnce() {
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t.Fatalf("Expected to be able to fill ports")
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}
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rports[i], err = a.AllocateNext()
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if err != nil {
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t.Fatalf("unexpected error: %v", err)
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}
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if rports[i] < 1 || rports[i] > 100 {
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t.Fatalf("unexpected allocated port: %d", rports[i])
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}
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a.lock.Lock()
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if bit := a.used.Bit(rports[i] - a.Base); bit != 1 {
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a.lock.Unlock()
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t.Fatalf("unexpected used bit for allocated port: %d", rports[i])
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}
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a.lock.Unlock()
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}
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if a.fillPortsOnce() {
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t.Fatalf("Expected to be unable to fill ports")
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}
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if reflect.DeepEqual(ports, rports) {
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t.Fatalf("expected re-allocated ports to be in a somewhat random order")
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}
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}
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