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126 lines
4.3 KiB
126 lines
4.3 KiB
#include <ATen/ATen.h>
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#include <ATen/AccumulateType.h>
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#include <ATen/cuda/CUDAContext.h>
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#include <ATen/cuda/Exceptions.h>
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// Another possibility:
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// #include <torch/all.h>
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#include <assert.h>
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// Stringstream is a big hammer, but I want to rely on operator<< for dtype.
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#include <sstream>
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#include "multi_tensor_apply.cuh"
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#include "common/micros.h"
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#define BLOCK_SIZE 512
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#define ILP 4
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template <typename T>
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__device__ __forceinline__ bool is_aligned(T *p) {
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return ((uint64_t)p) % (ILP * sizeof(T)) == 0;
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}
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template <typename T>
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__device__ __forceinline__ void load_store(T *dst, T *src, int dst_offset,
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int src_offset) {
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typedef
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typename std::aligned_storage<ILP * sizeof(T), ILP * alignof(T)>::type LT;
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((LT *)dst)[dst_offset] = ((LT *)src)[src_offset];
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}
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template <typename in_t, typename out_t>
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struct ScaleFunctor {
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__device__ __forceinline__ void operator()(int chunk_size,
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volatile int *noop_gmem,
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TensorListMetadata<2> &tl,
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float scale) {
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// I'd like this kernel to propagate infs/nans.
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// if(*noop_gmem == 1)
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// return;
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int tensor_loc = tl.block_to_tensor[blockIdx.x];
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int chunk_idx = tl.block_to_chunk[blockIdx.x];
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int n = tl.sizes[tensor_loc];
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in_t *in = (in_t *)tl.addresses[0][tensor_loc];
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in += chunk_idx * chunk_size;
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out_t *out = (out_t *)tl.addresses[1][tensor_loc];
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out += chunk_idx * chunk_size;
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n -= chunk_idx * chunk_size;
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bool finite = true;
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in_t r_in[ILP];
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out_t r_out[ILP];
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// to make things simple, we put aligned case in a different code path
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if (n % ILP == 0 && chunk_size % ILP == 0 && is_aligned(in) &&
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is_aligned(out)) {
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for (int i_start = threadIdx.x;
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i_start * ILP < n && i_start * ILP < chunk_size;
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i_start += blockDim.x) {
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// load
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load_store(r_in, in, 0, i_start);
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#pragma unroll
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for (int ii = 0; ii < ILP; ii++) {
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r_out[ii] = static_cast<float>(r_in[ii]) * scale;
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finite = finite && isfinite(r_in[ii]);
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}
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// store
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load_store(out, r_out, i_start, 0);
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}
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} else {
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// Non-divergent exit condition for __syncthreads, not necessary here
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for (int i_start = 0; i_start < n && i_start < chunk_size;
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i_start += blockDim.x * ILP) {
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#pragma unroll
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for (int ii = 0; ii < ILP; ii++) {
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r_in[ii] = 0;
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int i = i_start + threadIdx.x + ii * blockDim.x;
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if (i < n && i < chunk_size) r_in[ii] = in[i];
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}
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// note for clarification to future michael:
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// From a pure memory dependency perspective, there's likely no point
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// unrolling the write loop, since writes just fire off once their LDGs
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// arrive. Put another way, the STGs are dependent on the LDGs, but not
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// on each other. There is still compute ILP benefit from unrolling the
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// loop though.
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#pragma unroll
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for (int ii = 0; ii < ILP; ii++) {
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r_out[ii] = static_cast<float>(r_in[ii]) * scale;
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finite = finite && isfinite(r_in[ii]);
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}
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#pragma unroll
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for (int ii = 0; ii < ILP; ii++) {
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int i = i_start + threadIdx.x + ii * blockDim.x;
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if (i < n && i < chunk_size) out[i] = r_out[ii];
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}
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}
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}
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if (!finite)
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*noop_gmem =
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1; // Blindly fire off a write. These will race but that's ok.
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}
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};
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void multi_tensor_scale_cuda(int chunk_size, at::Tensor noop_flag,
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std::vector<std::vector<at::Tensor>> tensor_lists,
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float scale) {
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using namespace at;
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// The output (downscaled) type is always float.
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// If build times suffer, think about where to put this dispatch,
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// and what logic should be moved out of multi_tensor_apply.
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DISPATCH_FLOAT_AND_HALF(
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tensor_lists[0][0].scalar_type(), 0, "multi_tensor_scale_cuda",
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DISPATCH_FLOAT_AND_HALF(
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tensor_lists[1][0].scalar_type(), 1, "multi_tensor_scale_cuda",
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multi_tensor_apply<2>(BLOCK_SIZE, chunk_size, noop_flag, tensor_lists,
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ScaleFunctor<scalar_t_0, scalar_t_1>(),
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scale);))
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AT_CUDA_CHECK(cudaGetLastError());
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// AT_CUDA_CHECK(cudaDeviceSynchronize());
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}
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